{"id":112431,"date":"2025-06-18T14:34:00","date_gmt":"2025-06-18T06:34:00","guid":{"rendered":"https:\/\/www.ioiotimes.com\/?p=112431"},"modified":"2025-06-18T19:35:09","modified_gmt":"2025-06-18T11:35:09","slug":"amd-spartan-ultrascale-fpga%e9%96%8b%e5%a7%8b%e9%87%8f%e7%94%a2%e5%87%ba%e8%b2%a8%ef%bc%8c%e9%ab%98i-o%e3%80%81%e4%bd%8e%e5%8a%9f%e8%80%97%e5%8f%8a%e6%9c%80%e5%85%88%e9%80%b2","status":"publish","type":"post","link":"https:\/\/www.ioiotimes.com\/?p=112431","title":{"rendered":"AMD Spartan\u2122 UltraScale+\u2122 FPGA\u958b\u59cb\u91cf\u7522\u51fa\u8ca8\uff0c\u9ad8I\/O\u3001\u4f4e\u529f\u8017\u53ca\u6700\u5148\u9032\u7684\u5b89\u5168\u529f\u80fd\uff0c\u9069\u7528\u65bc\u6210\u672c\u654f\u611f\u578b\u908a\u7de3\u61c9\u7528"},"content":{"rendered":"\n

AMD \u5f88\u9ad8\u8208\u5ba3\u5e03\uff0cSpartan\u2122 UltraScale+\u2122<\/a>\u6210\u672c\u6700\u4f73\u5316\u7cfb\u5217\u7684\u9996\u6279\u5143\u4ef6\u73fe\u5df2\u6295\u5165\u91cf\u7522\uff01\u4e09\u6b3e\u6700\u5c0f\u578b\u7684\u5143\u4ef6\uff0dSU10P\u3001SU25P \u548c SU35P\uff0c\u76ee\u524d\u5df2\u958b\u653e\u8a02\u8cfc\uff0c\u4e26\u5728\u00a0AMD Vivado\u2122\u8a2d\u8a08\u5957\u4ef62025.1<\/a> \u4e2d\u63d0\u4f9b\u91cf\u7522\u5143\u4ef6\u652f\u63f4\u3002<\/p>\n\n\n

\n
\"\"<\/figure><\/div>\n\n\n

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AMD\u6210\u672c\u6700\u4f73\u5316\u7522\u54c1\u7d44\u5408<\/a>\u4e2d\u7684\u65b0\u54c1\u5c08\u70ba\u9700\u8981\u9ad8 I\/O\u3001\u4f4e\u529f\u8017\u548c\u6700\u5148\u9032\u5b89\u5168\u529f\u80fd\u7684\u6210\u672c\u654f\u611f\u578b\u908a\u7de3\u61c9\u7528\u800c\u6253\u9020\uff0c\u70ba\u7d93\u904e\u9a57\u8b49\u7684 UltraScale+\u2122 FPGA \u548c\u81ea\u884c\u8abf\u9069 SoC \u7522\u54c1\u7d44\u5408\u5e36\u4f86\u4e86\u73fe\u4ee3\u5316\u7684\u9023\u63a5\u80fd\u529b\u3001\u5f8c\u91cf\u5b50\u5bc6\u78bc\u7b49\u529f\u80fd\u3002<\/p>\n\n\n\n

\u9996\u6279\u6700\u4f4e\u5bc6\u5ea6\u5143\u4ef6\u7684\u91cf\u7522\u51fa\u8ca8\uff0c\u6a19\u8a8c\u8457\u7d93\u904e\u9a57\u8b49\u7684\u5c0f\u578b FPGA \u89e3\u6c7a\u65b9\u6848\u5728\u5165\u9580\u53ca\u4e2d\u968e\u5e02\u5834\u7684\u91cd\u8981\u91cc\u7a0b\u7891\u3002<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

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\u70ba\u5feb\u901f\u4e0a\u5e02\u5960\u5b9a\u5805\u5be6\u57fa\u790e<\/strong><\/strong><\/h3>\n\n\n\n

\u5c0b\u6c42\u6210\u672c\u6700\u4f73\u5316\u3001\u7dca\u6e4a\u578b FPGA \u7684\u5de5\u7a0b\u5e2b\u4e5f\u671f\u671b\u7c21\u55ae\u6613\u7528\u6027\u4ee5\u53ca\u5feb\u901f\u7684\u4e0a\u5e02\u6642\u7a0b\u3002\u4ed6\u5011\u9700\u8981\u53ef\u7a0b\u5f0f\u5316\u8a2d\u8a08\u908f\u8f2f\u3001\u9ad8 I\/O\u3001\u5f37\u5927\u7684\u5b89\u5168\u6027\u4ee5\u53ca\u4e16\u754c\u7d1a\u7684\u53ef\u9760\u6027\u3002\u6b64\u5916\uff0c\u4ed6\u5011\u66f4\u9700\u8981\u80fd\u5920\u5be6\u73fe\u4e00\u9375\u5f0f\u6642\u5e8f\u6536\u6582\u548c\u5feb\u901f\u9664\u932f\u529f\u80fd\u7684\u5de5\u5177\u3002\u6700\u91cd\u8981\u7684\u662f\uff0c\u4ed6\u5011\u9700\u8981\u4f4e\u98a8\u96aa\u7684\u4e0a\u5e02\u8def\u5f91\u3002Spartan UltraScale+ FPGA \u7531\u696d\u754c\u9818\u5c0e\u8005\u63a1\u7528\u7d93\u904e\u9a57\u8b49\u7684 UltraScale+ \u6280\u8853\u6253\u9020\u8a3b1<\/sup>\uff0c\u6b63\u80fd\u6eff\u8db3\u9019\u4e9b\u9700\u6c42\u3002<\/p>\n\n\n\n

\u900f\u904e Spartan UltraScale+ FPGA\uff0cAMD \u4ee5\u5176\u6210\u719f\u7684 UltraScale+ FPGA \u67b6\u69cb\u8457\u624b\uff0c\u8a72\u67b6\u69cb\u63d0\u4f9b\u4e86\u6548\u80fd\u8207\u4f4e\u529f\u8017\u7684\u51fa\u8272\u5e73\u8861\uff0c\u4e26\u5177\u6709\u8f03\u9577\u7684\u7522\u54c1\u751f\u547d\u9031\u671f\u3002\u5728\u9023\u63a5\u6027\u65b9\u9762\uff0cSpartan UltraScale+ FPGA \u7d50\u5408\u4e86\u9ad8\u5bc6\u5ea6\u8f38\u5165\uff0f\u8f38\u51fa\uff08HDIO\uff09\u4ee5\u5be6\u73fe\u8c50\u5bcc\u7684 3.3V I\/O \u652f\u63f4\uff0c\u540c\u6642\u9084\u6709\u65b0\u7684\u9ad8\u901f XP5IO\uff0c\u4e26\u63d0\u4f9b\u696d\u754c\u6700\u9ad8\u7684 I\/O \u8207\u908f\u8f2f\u6bd4\u4f8b\u8a3b2<\/sup>\uff0c\u7531\u9ad8\u6548\u80fd\u548c\u4f4e\u529f\u8017\u67b6\u69cb\u63d0\u4f9b\u652f\u63f4\u3002<\/p>\n\n\n\n

\u8a2d\u8a08\u4eba\u54e1\u9084\u53ef\u4ee5\u900f\u904e AMD Vivado \u8a2d\u8a08\u5957\u4ef6\u5be6\u73fe\u5feb\u901f\u8a2d\u8a08\u6536\u6582\u548c\u8de8\u5c08\u6848\u7684\u8f15\u9b06\u91cd\u8907\u4f7f\u7528\uff0c\u8a72\u8a2d\u8a08\u5957\u4ef6\u652f\u63f4\u8d85\u904e 160 \u6b3e AMD FPGA \u548c\u81ea\u884c\u8abf\u9069 SoC\u3002\u5728\u677f\u7d1a\u63a7\u5236\u548c I\/O \u64f4\u5c55\u7b49\u61c9\u7528\u4e2d\uff0c\u6642\u8108\u901f\u5ea6\u5f88\u5c11\u8d85\u904e 150 MHz\uff0c\u4f7f\u7528\u8005\u53ef\u4ee5\u5be6\u73fe\u4e00\u9375\u5f0f\u6642\u5e8f\u6536\u6582\uff0c\u5f9e\u800c\u5feb\u901f\u5b8c\u6210\u8a2d\u8a08\u53cd\u8986\u904b\u7b97\u8a3b3<\/sup>\u3002\u5c0d\u65bc\u9700\u8981\u66f4\u9ad8\u6548\u80fd\u7684\u6a5f\u5668\u8996\u89ba\u3001\u5de5\u696d\u548c\u91ab\u7642\u61c9\u7528\uff0cSpartan UltraScale+ FPGA \u80fd\u63d0\u4f9b\u6bd4\u7af6\u722d\u5c0d\u624b\u5169\u500b\u901f\u5ea6\u7b49\u7d1a\u7684\u512a\u52e2\u8a3b4<\/sup>\u3002<\/p>\n\n\n\n

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\u70ba\u6210\u672c\u654f\u611f\u578b\u61c9\u7528\u63d0\u4f9b\u5168\u65b0\u529f\u80fd<\/strong><\/strong><\/h3>\n\n\n\n

\u5728\u6b64\u7d93\u904e\u9a57\u8b49\u7684\u57fa\u790e\u4e0a\uff0cSpartan UltraScale+ FPGA \u70ba AMD \u6210\u672c\u6700\u4f73\u5316\u7522\u54c1\u7d44\u5408\u5e36\u4f86\u591a\u9805\u65b0\u9032\u5c55\uff1a<\/p>\n\n\n\n

\u2022\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u6700\u5148\u9032\u7684\u5b89\u5168\u6027\uff0c\u5167\u5efa\u786c IP\uff0c\u63a1\u7528 NIST \u8a8d\u8b49\u7684\u6f14\u7b97\u6cd5\u5be6\u73fe\u5f8c\u91cf\u5b50\u5bc6\u78bc\u3002\u9019\u4e0d\u50c5\u5be6\u73fe\u4e86\u5b89\u5168\u7684\u5143\u4ef6\u914d\u7f6e\uff0c\u66f4\u652f\u63f4\u4f7f\u7528\u8005\u5b58\u53d6\u5c08\u7528\u5bc6\u78bc\u8cc7\u6e90\uff0c\u5305\u62ec\u771f\u4e82\u6578\u751f\u6210\u5668\uff08TRNG\uff09\u3001\u7269\u7406\u4e0d\u53ef\u8907\u88fd\u529f\u80fd\uff08PUF\uff09\u3001\u5b89\u5168\u96dc\u6e4a\u7b49\u3002
\u2022\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u6574\u5408\u5f0f\u8a18\u61b6\u9ad4\u63a7\u5236\u5668\uff0c\u652f\u63f4\u9ad8\u9054 4266 Mb\/s \u7684 LPDDR4X\/5\uff0c\u63a1\u7528 32 \u4f4d\u5143\u4ecb\u9762\uff0c\u53ef\u7bc0\u7701\u9ad8\u9054 15 kLC\uff0c\u8b93\u8a2d\u8a08\u4eba\u54e1\u80fd\u5920\u8f49\u5411\u66f4\u5c0f\u7684\u5143\u4ef6\uff0c\u9032\u4e00\u6b65\u964d\u4f4e\u529f\u8017\u548c\u6210\u672c\u3002
\u2022\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u5168\u65b0 XP5IO \u985e\u5225\u652f\u63f4\u9ad8\u9054 1.8 Gb\/s \u7684\u4f4e\u96fb\u58d3\u5dee\u5206\u8a0a\u865f\uff08LVDS\uff09\u30013.2 Gb\/s MIPI D-PHY \u53ca\u5176\u4ed6\u9ad8\u901f\u5dee\u5206\u4ecb\u9762\u3002
\u2022\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u7b26\u5408 PCIe\u00ae Gen4 \u6a19\u6e96\u7684\u786c IP\uff0c\u652f\u63f4\u7d42\u7aef\u548c\u6839\u57e0\u61c9\u7528\u3002
\u2022\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a08 \u901a\u9053 SPI \u4ecb\u9762\u652f\u63f4\uff0c\u53ef\u5f9e\u5916\u90e8\u5feb\u9583\u8a18\u61b6\u9ad4\u5be6\u73fe\u66f4\u5feb\u7684\u914d\u7f6e\u548c\u8cc7\u6599\u50b3\u8f38\u901f\u7387\u3002<\/p>\n\n\n\n

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\u5982\u540c\u5176\u4ed6 AMD \u6210\u672c\u6700\u4f73\u5316\u5143\u4ef6\uff0cSpartan UltraScale+ FPGA \u7684\u652f\u63f4\u5305\u542b\u5728\u514d\u8cbb\u7684 AMD Vivado \u8a2d\u8a08\u5957\u4ef6\u6a19\u6e96\u7248\u4e2d\uff0c\u53ef\u5728\u55ae\u4e00\u5de5\u5177\u4e2d\u5b8c\u6210\u5f9e\u6a21\u64ec\u5230\u9a57\u8b49\u7684\u6240\u6709\u5de5\u4f5c\u3002\u8acb\u81f3 AMD \u5b98\u65b9\u7db2\u7ad9\u4e0b\u8f09 Vivado\u8a2d\u8a08\u5957\u4ef6<\/a>\u3002<\/p>\n\n\n\n

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\u3000\u3000<\/p>\n\n\n\n

\u8a3b1\uff1a\u71df\u6536\u6578\u64da\uff0cOmida\u7af6\u722d\u683c\u5c40\u5de5\u5177CTL\u5b63\u5ea6\u534a\u5c0e\u9ad4\u5e02\u5834\u4efd\u984d\uff0c2023\u5e7411\u6708\u3002SUS-012
\u8a3b2\uff1a\u6839\u64daAMD\u5167\u90e8\u65bc2023\u5e7412\u6708\u7684\u5206\u6790\uff0c\u6bd4\u8f03AMD Spartan UltraScale+ FPGA\u8207\u524d\u5e7e\u4ee3AMD\u6210\u672c\u6700\u4f73\u5316FPGA\u7684\u7e3dI\/O\u8207\u908f\u8f2f\u55ae\u5143\u6bd4\u3002SUS-001
\u8a3b3\uff1a\u6839\u64daAMD\u65bc2024\u5e749\u6708\u7684\u4f48\u5c40\u8207\u7e5e\u7dda\u6e2c\u8a66\uff0c\u4f7f\u752826\u500b\u958b\u653e\u6838\u5fc3\u8a2d\u8a08\uff0c\u900f\u904eAMD Vivado 2024.1\u548cLattice Radiant Software 2024.1\u5728\u9810\u8a2d\u6a21\u5f0f\u4e0b\u7de8\u8b6f\uff0cArtix UltraScale+ AU10P\u5143\u4ef6\u8207Lattice Mach LFMXO5\u5143\u4ef6\u5728150 MHz FMAX\u76ee\u6a19\u4e0b\u9032\u884c\u6bd4\u8f03\uff1b\u4ee5\u53caKintex UltraScale+ KU5P\u5143\u4ef6\u8207Lattice Avant E70\u5143\u4ef6\u5728200 MHz FMAX\u76ee\u6a19\u4e0b\u9032\u884c\u6bd4\u8f03\u3002\u4f48\u5c40\u8207\u7e5e\u7dda\u6548\u80fd\u6703\u56e0\u5143\u4ef6\u3001\u8a2d\u8a08\u3001\u914d\u7f6e\u548c\u5176\u4ed6\u56e0\u7d20\u800c\u7570\u3002VIV-011
\u8a3b4\uff1a\u6839\u64daAMD\u65bc2024\u5e747\u6708\u7684\u5206\u6790\uff0c\u8a08\u7b97(16\u5948\u7c73) AMD Artix UltraScale+ AU7P\u548c(16\u5948\u7c73) Lattice Avant E70\u6240\u6709\u53ef\u7528\u901f\u5ea6\u7b49\u7d1a\u7684FMAX\u826f\u7387\u3002\u5be6\u969b\u7d50\u679c\u6703\u56e0\u67b6\u69cb\u3001\u5143\u4ef6\u3001\u901f\u5ea6\u7b49\u7d1a\u3001\u5c01\u88dd\u5c3a\u5bf8\u3001\u8a2d\u8a08\u3001\u914d\u7f6e\u548c\u5176\u4ed6\u56e0\u7d20\u800c\u7570\u3002AUS-009<\/sub><\/p>\n\n\n\n

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\u3000\u3000\u3000\u3000<\/p>\n\n\n\n


\ud83d\udfe6\u73fe\u5728\u5c31\u52a0\u5165 ioioTIMES \u81c9\u66f8\u7c89\u7d72\u5718 \u66f4\u591a\u4e92\u52d5\u3001\u66f4\u591a\u597d\u5eb7\u650f\u62b5\u52a0!!
\ud83d\udfe6\u6211\u5011\u6709LINE TODAY<\/a>\u983b\u9053\u4e86\uff0c\u5feb\u4f86\u8ffd\u8e2a\u6211\u5011\u5427!!–\u6700\u65b0\u79d1\u6280\u65b0\u805e \u76e1\u5728\u4f60<\/strong>\u624b<\/h4>\n","protected":false},"excerpt":{"rendered":"

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